A Translation Look-aside Buffer (TLB) is a table in a computer processor's memory that contains information about locations in memory the processor has accessed recently or is soon to access. The table cross-references a program's virtual addresses (such as variables names) with the corresponding absolute addresses in physical memory. Storing these cross-references avoids re-translation of recently used addresses. The TLB enables faster computing because it allows the address processing to take place independent of the normal address-translation pipeline. A TLB is commonly a fully associative cache and is also referred to as an address translation cache. A typical TLB contains anywhere from 32 to 1024 entries.
A TLB is inserted in a critical access path between the Central Processing Unit and a physical memory, and so needs to be very fast. Adding error checking to a TLB, such as parity checks and error correction codes (ECC's), adds too much delay to the caching process, so error checking is not performed until a TLB entry is used. As a consequence, an error in a TLB entry is signaled too late to have proper containment and may be fatal in a processor design.